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Lattice Semiconductor
CSIX-to-PI40 IP Core User’s Guide
Introduction
Lattice’s CSIX-to-PI40 core provides a customizable solution allowing a CSIX interface to Agere Systems’ PI40
switch fabric. This user’s guide explains the functionality of the CSIX-to-PI40 core and how it can be implemented
to provide that interface.
The CSIX-to-PI40 core comes with the documents and ?les listed below:
? Data sheet
? Encrypted gate level netlist
? Secured RTL simulation model
? Core instantiation template
Features
? Implements a CSIX-L1-to-PI40 Bridge
? Supports standard 32-bit, 100MHz CSIX-L1 interfaces.
? Supports PI40 dual-SERDES interface links
? Interfaces on PI40 side to ORSO82G5 embedded core.
? Supports CSIX Idle, Unicast, Multicast ID and Flow Control frames.
? Interprets CSIX-L1 Cframe header, translates relevant information to PI40. Fabric Input Port Interface (FIPI)
compatible header and encapsulates Cframes in PI40 payload for transport through fabric.
? Interprets PI40 Fabric Output Port Interface (FOPI) Format 1 header, translates appropriate cell type and ?ow
control information and extracts Cframes from PI40 payload.
? Supports CSIX/PI40 ?ow control interworking; generates CSIX-L1 Flow Control Cframes in egress direction.
? Ingress data Cframe FIFO size of 1,024 bytes.
? Egress data Cframe FIFO size of 4,096 bytes.
? Egress control Cframe FIFO size of 1,024 bytes.
? Parameterizable PI40 user payload size (64, 72 or 80 octets) and corresponding Cframe
MAX_FRAME_PAYLOAD_SIZE (56, 64 or 72 octets, respectively).
? Parameterizable number of CSIX/PI40 link instantiations (one or two).
? Parameterizable support for SERDES protection switching.
? Parameterizable type of I/O buffers for CSIX interface (LVCMOS or HSTL).
? Internal register set for control and status management.
? 8-bit register interfacing via built-in ORCA ? System Bus.
General Description
As stated by the CSIX Forum, the CSIX standard de?nes the physical and message layers of the interconnect
between traf?c managers (TM) and the switching fabric. The CSIX interface is designed to support a wide variety of
system architectures and markets; and provides a framework with a common set of mechanisms for enabling a fab-
ric and a TM to communicate. This includes unicast addressing for up to 4,096 fabric ports, and multiple traf?c
classes that isolate data going to the same fabric port. Link level ?ow control is in-band and broken into data and
control queues to isolate traf?c based on this granular type. Flow control between the fabric and TM is de?ned and
is relative to both fabric port and class. Three multicast approaches are de?ned. The interface assumes cell seg-
mentation in the TM, but allows compression of the transfer.
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